The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Many packet-based communication networks include various devices, such as bridges, routers, etc., that operate on packets according to information contained in headers of the packets. Digital hardware within these devices typically processes various fields within the packet headers in order to perform different functions. To this end, certain basic processing operations are commonly performed, such as parsing a particular field of a packet header (e.g., identifying and extracting the field so that it may be sent elsewhere for further processing), and/or modifying the field by replacing one or more bits or bytes of the field with new values. As one of many possible examples, a packet processing unit within a router device may parse a destination medium access control (MAC) address field of a packet header, and send the destination MAC address to another processing unit within the router for further processing (e.g., to compare the destination MAC address with the MAC address of the router). As another example, a packet processing unit within a router may modify a source MAC address field of a packet header by setting the field value to the MAC address of the router before forwarding the packet to another device.
Typically, small interface widths (e.g., wire, trace, or pin counts) are desirable between different packet processing units within a device, or between packet processing units of multiple devices, in order to satisfy cost and size constraints. Packet header sizes, however, have tended to increase over time due to advances in technology. As a result, packet headers are commonly sent over interfaces that are narrower than the header size, requiring that the packet header be sent over the course of multiple transactions or clock cycles. For example, a 64 byte interface may require three transactions to receive an entire 190 byte header (i.e., in successive header portions of 64 bytes, 64 bytes, and 62 bytes). Parsing or modifying header fields in such cases has traditionally been accomplished by accumulating the header portions in registers until the entire packet header has been received, at which point the desired processing operation is performed. This approach, however, generally suffers from various drawbacks. For example, the accumulation of the header portions typically requires a significant amount of storage area (e.g., a large number of flip-flop cells) in order to store the entire header, and introduces a packet transmission latency that can be substantial for larger header sizes sent over a larger numbers of transactions. Moreover, the traditional approach can require complex circuitry occupying a large area, with the design of much of the circuitry being highly dependent on the maximum header size.